The main feature of the IC Industry is that winners can take all the benefits and credit. For instance, an industry giant like Intel profits may rise up to 60% at its peak.
Yet, what is the actual cost of those CPUs, accordingly, over hundreds or even thousands of units?
The Hardware Cost Structure of Chips
The cost structure of chips includes both the cost of hardware and the cost of design.
The cost of hardware part can be represented by an equation:
Hardware cost = (Die costs+Testing costs+Packaging costs+Packing costs)/Total Functional Units per Wafer
Going from silica to silicon chip on the market requires going through the preparation of industrial silicon to electronic grade silicon, then cutting and polishing into wafers. Wafers are the raw materials for chip fabrication. The wafer cost can be understood as the cost of all raw materials used in the chip fabrication. Under normal circumstances, especially when production numbers are great enough — calculating for billions of units — and with proprietary intellectual property rights, materials make up the highest proportion of the wafer cost.
Packaging is the process in which the substrate, core, and heatsink are stacked together to form a CPU. The packaging cost is the capital required for this procedure. Under normal conditions of high output, packaging costs are 5% to 25% of the cost of hardware. Whereas, some IBM chip packaging is 50% and even up to 70% at the highest.
Testing can identify the key characteristics of each processor, such as the highest frequency, power consumption, and heat dissipation, etc., and determine the grade of the processor. However, if the chip production output is large enough, the test cost is negligible.
Packing costs is the cost based on the requirements of different process technology. For example, 40/28 nm process technology is already very mature, the cost is decreasing. 40 nm low-power consumption process technology costs US$2 million, while 28 nm SOI technology costs $4 million and 28nm HKMG costs $6 million.
Mask Aligner
However, if the chip production is in the hundred millions of units, even when the mask cost is as high as $1 billion, the cost allocated for each chip is only $10. From this perspective, it demonstrates why giants like Apple can still earn fortunes using the most advanced and expensive process technology from TSMC and Samsung and, furthermore, why IC design has a winner takes all characteristic.
TSMC created the semiconductor Dedicated IC Foundry business model when it was founded in 1987. TSMC served about 470 customers and manufactured more than 8,900 products for various applications covering a variety of computer, communications, and consumer electronics market segments. TSMC is headquartered in the Hsinchu Science Park, Taiwan, and has account management and engineering service offices in China, Europe, India, Japan, North America, and, South Korea. Feel free to connect to an expert from TSMC on HWTrek here.
Like foundries undertaking photolithography, the costs required for etching, ion implantation, metal deposition, metal layering, interconnecting, wafer testing and cutting, core packaging, level testing and other steps, as well as all the equipment and depreciation costs, are counted into the testing cost, packaging cost, and mask cost.
4030 / AMD: EUROPA, DEUTSCHLAND, SACHSEN, DRESDEN (EUROPE, GERMANY, SAXONY), 17.12.2006: AMD Saxony, Wafer 65 nm Ballpeenhammer, Dual Core -AMD-300 mm Wafer manufactured by GLOBALFOUNDRIES
Die Cost
Due to wafer processing when die are cut, the wafer is not completely utilized. Because of the problem of yield, the formula for calculating die cost is:
Die cost = wafer cost / ( number of die per wafer x the number of die produced)
Intel Silverthorne Wafer
Because the wafer is circular and the die is rectangular, it will inevitably lead to waste. Therefore the number of die that each wafer can yield, can not be derived by simply divided by the area of the wafer by the area of a die, and to the following formula:
Number of die per wafer = (wafer area/die area)－ (wafer circumference/ square root of (2 x die area))
Die yield, process complexity, and the number of defects per unit area are closely related. Die yield can be calculated with the following formula:
Die yield = the negative A root of (1+B x die cost/A)
A is the process complexity. For example, the complexity of a 40 nm process low-power consumption CPU-X is considered to be 2 to 3.
B is the number of defects per unit area. The defect value for a 40 nm process CPU-X unit area is between 0.4 to 0.6.
Assuming the CPU-X die is 15.8 mm long and 12.8 mm wide with an area of about 200 square millimeters, a 12-inch wafer is about 70,000 square millimeters. Therefore, a wafer can yield 299 die of CPU-X. Supposing the process complexity (A) is 3 with defect rate (B) of 0.5, the yield is 49%. Thus, a 12-inch wafer can yield 146 good CPU-X die. The cost of each die would be $28 for a 12-inch wafer costing $4,000.
UMC is a leading global semiconductor foundry that provides advanced technology and manufacturing for applications spanning every major sector of the IC industry. UMC’s robust foundry solutions allow chip designers to leverage the company’s leading-edge processes, which include 28 nm poly-SiON and gate-last High-K/Metal Gate technology, mixed signal/RFCMOS, and a wide range of specialty technologies. Production is supported through 10 wafer manufacturing facilities that include two advanced 300 mm fabs. The company employs over 17,000 people worldwide and has offices in Taiwan, Japan, Korea, China, Singapore, Europe, and the United States. Connect with an expert from UMC on the HWTrek platform here.
The Cost of the Hardware of Chips
There is no specific formula for the cost of packaging and testing. The test cost is approximately in proportion to the square of the number of pins, while the package cost is approximately in proportion to the cube of the number of pins and power consumption. If CPU-X uses a low-power consumption 40 nm process custom chip, the test cost is about $2 and package cost is $6.
Chip Package Styles
Mask cost would be US$2 million for low-power 40 nm process technology. If the production of CPU-X reaches 100,000, the mask cost is $2, and package cost $6, and die cost is $28, the total hardware chip cost would be $85: (20+2+6)/0.49 + 28 = 85.
Under the same yield, the use of more advanced process technology will increase the cost of the chip hardware. However, as long as production is large enough, the original high costs can be amortized by the huge volumes and cost of the chip can be greatly reduced as a result.
Triad Semiconductor is the expert in custom IC design and supply chain management. Our mission is to enable the success of our customers through highly differentiated IC solutions that reduce cost, noise, size, weight, and power and increase IP protection, performance, manufacturability, and reliability. Connect with an expert from Triad Semiconductor on HWTrek to get more information about their IC design services.
Chip Pricing
While hardware costs are relatively defined, design costs are more complicated. Design costs include the costs of engineers’ salaries, EDA development tools, equipment, and office space, etc. In addition, IP costs are a significant piece of the total design cost.
According to international standard cost to price ratio strategy of 8:20 for lower profit IC design companies (that is hardware cost of $8 to a price of $20), the price of CPU-X would be $212 for a production of 100,000 units. This should not be considered expensive, in fact, it is very low in comparison to the pricing ratios for Intel and AMD, which have historically been 8:35 and 8:50, respectively.
Source: Leiphone
Author: Tieliu
Translator: William Albano
